Compiler-directed Dynamic Voltage and Frequency Scaling for Cpu Power and Energy Reduction by Chung-hsing Hsu

OF THE DISSERTATION COMPILER-DIRECTED DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR CPU POWER AND ENERGY REDUCTION by Chung-Hsing Hsu Dissertation Director: Ulrich Kremer The high power consumption of a processor is becoming a critical problem for both battery-powered devices and high-performance computers. It reduces circuit reliability, complicates the cooling technology, shortens the battery lifetime, and increases the production and operation costs of a CPU. One effective technique, called dynamic voltage scaling (DVS), achieves CPU power reduction through lowering the CPU supply voltage and clock frequency at runtime. It is effective because the CPU power is proportional to the clock frequency and to the square of the supply voltage. However, the CPU power savings come at the cost of degraded performance due to the slower clock frequency. Furthermore, the longer the CPU runs, the more power other computer components (e.g., disk and screen) will consume; not to mention that a user may not be willing to sacrifice any performance. Therefore, DVS should only be applied when it will not noticeably affect performance. In this thesis I will present investigations on how compiler techniques can be used to minimize CPU power and energy consumption with almost no performance penalty. A compile-time DVS algorithm is proposed that uses a profile-driven program analysis to identify and slow down program regions whose performance bottleneck is not in